In recent years, MOSFET. (metal oxide semiconductor field effect transistor) as a semiconductor device has been extremely miniaturized and highly integrated. Concurrent-to this trend, the thickness of a gate dielectric film has been reduced from the point of view of securing the driving current and saving power consumption. However, the value of parasitic capacitance resulted from the depletion generated in a gate electrode composed of polysilicon due to the reduction of the thickness of gate dielectric films has not been able to ignored, thereby arising problems in the highly integration and power saving of MOSFETs.
In order to cope with such problems, the use of silicon germanium (hereafter abbreviated to “SiGe”) for a gate electrode has been proposed. The use of a SiGe film in, the gate electrode of an MOSFET can improve the activation rate of conductive impurities (e.g., boron) in the gate electrode, inhibit the depletion of the gate electrode, thus reducing the parastic capacitance. This allows the use of a gate dielectric film with an increased thickness and the reduction of gate leakage current.
Although the width of the gate electrode (hereafter referred to as “gate length”) must be reduced with the above-described miniaturization of the MOSFET, the thickness of the gate electrode must also be reduced from the point of view of the stability and the processing accuracy of gate wiring patterns. For example, according to the ITRS Roadmap of 2001 Edition, the thickness of agate electrode must be reduced to 35 nm to 70 nm in a semiconductor device of the 35-nm-gate-length generation.
In order to lower the resistance of a gate electrode, a silicide film may be formed above the SiGe film. In this case, there is a problem of the occurrence of silicide cohesion and defective resistance caused by Ge in the SiGe film during the formation of the cobalt silicide film. In order to solve this problem, there has been proposed to form a thick cap Si film on the SiGe film, and to adjust the Ge concentration in the surface of the cap Si film to 2% of less (e.g., refer to Japanese Patent Laid-Open No. 2002-261274 (Page 5, FIG. 1)).
In next-generation semiconductor devices, as described above, the thickness reduction of the SiGe film as the gate electrode is demanded. Furthermore, when a cap Si film is formed on the SiGe film to form a silicide film, since the thickness of the SiGe film must be the value of the entire thickness of the gate electrode minus the thickness of the silicon film, the SiGe film must further be thinned.
However, the own examinations by the present inventor revealed the occurrence of problems described below when the SiGe film is thinned.
FIGS. 13A to 13C are SEM photographs showing the cross section of the thinned SiGe film grown on a gate dielectric film composed of a SiO2 film. Specifically, FIG. 13A shows the case where the SiGe film of a thickness of 150 nm is formed, FIG. 13B shows the case where the SiGe film of a thickness of 50 nm is formed, and FIG. 13C shows the case where the SiGe film of a thickness of 20 nm is formed.
As FIG. 13A shows, when the SiGe film is relatively thick (150 nm), the continuous film free of voids is attained. However, as FIG. 13B shows, when the growth time is shortened to make the thickness of the SiGe film 50 nm, voids (refer to circled portions in FIG. 13B) generate in the SiGe film. When the growth time is further shortened to make the thickness of the SiGe film 20 nm, the film becomes discontinuous due to surface roughness as FIG. 13C shows.
When the SiGe film is thinned, as described above, there are problems that voids generate in the SiGe film during growing the grains of the SiGe film, or the SiGe film becomes discontinuous due to surface roughness of the SiGe film, that is, a defective SiGe film is produced. There are also problems that the conformation of the SiGe film varies due to heat treatment performed after the formation of the SiGe film, thus forming of a defective SiGe film.
If the above-described defective film is formed due to the thinning of the SiGe film, it is difficult to form the SiGe film having a uniform Ge content in the boundary between the gate dielectric film and the gate electrode. In addition, when a gate electrode is formed using dry etching, locally defective processing caused by the non-uniformity of the thickness of the SiGe film. Since the voids generated in the SiGe film causes variation in the wiring resistance of the gate wirings and the driving ability of the transistor, the yield of transistor manufacturing is affected.